Generally, a memory controller with a low density parity check (LDPC) decoding function converts data read from a nonvolatile semiconductor memory into a log-likelihood ratio (LLR) using an LLR table created in advance, and corrects an error included in the data.
A likelihood of write data (i.e., a correct bit value) corresponding to readout data varies depending upon a stress on a memory area of the readout data. There are typical stresses e.g., program disturb (PD), data retention (DR), and read disturb (RD). In accordance with such typical stresses, a plurality of LLR tables are pre-created. However, even when the LLR tables are prepared, it is difficult to adapt for all various stresses to which memory cells in the nonvolatile semiconductor memory may be subject. That is, even if the LLR tables are prepared in advance, it may be impossible to suppress a deterioration of error correctability under a part of given unexpected stress (e.g., a composite stress of the DR stress and RD stress).